During the last two decades there has been a great deal of interest in the use of multiple levels information transfer in order to increase signaling bandwidth. In general, signaling with multiple voltage levels uses lower fundamental frequency than binary signaling at the same data rate, offering the potential of higher performance in digital systems which have limited bandwidth. In that sense, in this paper, we propose a signaling technology based on combination of code division multiple access, CDMA, and pulse amplitude modulation, PAM, that exploits parallelism at on- and off-chip system level, resulting in higher information transfer over direct link. The CDMA logic uses different PN codes to separate the information carried on different bus lines over direct link, while PAM approach is based on multilevel signaling. The transceiver circuit has been developed using Xilinx FPGA technology for realization of the CDMA coder/decoder, and 0.35 mm CMOS four layers process technology for implementation of the 4-PAM coder/decoder block. Simulation results show that the effective communication bandwidth is 1.1 Gbps, with an average power consumption of 25 mW per single channel at 200 MHz operating frequency and power supply of 3.3 V.