This paper describes the architecture and performance of a high-resolution time–to–digital converter (TDC) based on a Vernier delay line. The TDC is used as a basic building block for time interval measurement in an ultrasonic liquid flowmeter. Operation of the TDC with 10ps LSB resolution and 1 ms input range has been simulated using library models for 1.2 µm double metal double–poly CMOS technology. The TDC operates at clock frequency of 200 MHz, and is composed of 500 delay–latch elements. The difference in delay between two chains, one for the start and the other for stop pulse, is controlled by the delay locked loop (DLL).