Programmable jitter generator based on voltage controlleddelay line

Authors: G. Jovanović, M. Stojčev, T. Nikolić, Z. Stamenković

Keywords: jitter; jitter generator; jitter classification

Abstract:

As CMOS technology has scaled, supply voltage have dropped, chip power consumption has increased, and clock frequency/data rates increase effects of jitter become critical and jitter budget get tighter. Knowing how to inject/isolate jitter components with the time convolution/correlation method will enhance designer ability to determine and locate the root causes so that one can then proceed to ‘beat down’ individual error components one at a time in order to improve system performance. Jitter can be decomposed into several components, each having specific sets of characteristics and root causes. This paper begins with a short review of jitter fundamentals including a discussion of the various random and deterministic jitter components, and injection method of jitter subcomponents into computer clock signal and/or communication data stream. The jitter injection technique gives test engineers an insight into how jitter components interact. In the rest of the paper, the global hardware structure of a jitter generator, which uses digital techniques, based on a voltage controlled delay line is described. A Xilinx xc3s500e-5fg320 FPGA chip is used to validate this design. The programmable jitter generator can be used in the jitter tolerance test for computer systems and jitter transfer function measurements in communication systems

References:

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