Interconnection architecture based on PAM and CDMA signaling technique
Authors: G.S. Jovanović, T.R. Nikolić, M.K. Stojčev
Keywords: Signaling Interconnect; CDMA&PAM direct link; multilevel data transfer
Abstract:
During the last two decades there has been a great deal of interest in the use of multiple levels information transfer in order to increase signaling bandwidth. In general, signaling with multiple voltage levels uses lower fundamental frequency than binary signaling at the same data rate, offering the potential of higher performance in digital systems which have limited bandwidth. In that sense, in this paper, we propose a signaling technology based on combination of code division multiple access, CDMA, and pulse amplitude modulation, PAM, that exploits parallelism at on- and off-chip system level, resulting in higher information transfer over direct link. The CDMA logic uses different PN codes to separate the information carried on different bus lines over direct link, while PAM approach is based on multilevel signaling. The transceiver circuit has been developed using Xilinx FPGA technology for realization of the CDMA coder/decoder, and 0.35 mm CMOS four layers process technology for implementation of the 4-PAM coder/decoder block. Simulation results show that the effective communication bandwidth is 1.1 Gbps, with an average power consumption of 25 mW per single channel at 200 MHz operating frequency and power supply of 3.3 V.
References:
[1] J. Kim, I. Verbauwhede, M-C Frank Chang, “Design of an Interconnect Architecture and
Signaling Technology for Parallelism in Communication”, IEEE Transactions on Very Large
Scale Integration (VLSI) Systems, Vol. 15, No. 8, pp.881-893, August 2007.
[2] S. Pasrisha, N. Dutt, On-Chip Communication Architectures: System-on-Chip Interconnect,
Morgan Kaufmann, Boston, 2008.
[3] D. Foley, M. Flynn, “A Low-Power 8-PAM Serial Transceiver in 0.5 µm Digital CMOS”,
IEEE Journal of Solid-State Circuits, Vol. 37, No. 3, pp.310-316, March 2002.
[4] Amirkhany A., Abbasfar, A., Savoj, J., Jeeradit, M., Garlepp, B., Kollipara R., Stojanovic,
V., Horowitz, M., “A 24Gb/s Software Programmable Analog Multi-Tone Transmitter”, IEEE
Journal of Solid-State Circuits, Vol. 43, No. 4, April 2008, pp. 999-1009
[5] TST. Mak, P. Sedcole, P. Y. K. Cheung, W. Luk, “On-FPGA communication architectures
and design factors”, In: Proc. International Conference on Field Programmable Logic and
Applications, Vol 1, pp. 1-8, Madrid, 2006.
[6] M. Mitic, M. Stojcev, “An overview of on-chip buses”, Facta Universitatis, Series: Electronics
and Energetics, Vol.19, No.3, pp.405-428, November 2006.
[7] S. Dey, K. Lahiri, A. Raghunathan, “Design of communication architectures for high performance and energy-efficient systems-on-chips”, In: Jerraya AA, Wolf W, editors. Multi-processor Systems-on-Chips, Morgan Kaufman, pp. 187-222, San Francisco, 2004.
[8] L. Benini, G. De Micheli, Networks on Chips, Elsevier, Boston, 2006.
[9] A. Jantsch, H. Tenhunen, Introduction. In: Jantsch A, Tenhunen H, editors. Networks on Chip,
Kluwer Academic Publishers, pp. 1-24, Boston, 2003.
[10] M-c Frank Chang, I. Verbauwhede, C. Chien, Z. Xu, J. Kim, J. Ko, Q. Gu, B-C Lai, “Advanced RF/Based Interconnect Schemes for Inter- and Intra-ULSI Communications”, IEEE
Transactions on Electron Devices, Vol. 52, No. 7, pp.1271-1285, July 2005.
[11] J.Y. Sim, Y.S. Sohn, S.C. Heo, H.J. Park, S.I. Cho, “A 1-Gb/s Bidirectional I/O Buffer Using
the Current Mode Schemes”, IEEE Journal of Solid-State Circuits, Vol. 34, No. 4, pp.1271-
1285, April, 1999.
[12] W-H. Chen, G-K. Debug, J-W. Chen, S-I. Liu, “A CMOS 400/Mb/s Serial Link for ASMemory Systems Using a PWM Scheme”, IEEE Journal of Solid-State Circuits, Vol. 36, No.
10, pp. 1498-1505, October 2001